forked from eggy/eifueo
ece124: look man i dunno either
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@@ -462,6 +462,68 @@ An **equivalent state** is such that each input has the same output and an equiv
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2. For each state, if not all states transition to the same group, subgroup them such that they do
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3. Repeat as necessary
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## Asynchronous sequential circuits
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ASCs hae no clocks, relying on feedback from outputs for their memory effect.
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!!! warning
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ASCs break down if any of these assumptions fail.
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- Only one input is allowed to change at a time
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- Inputs change only after the circuit stabilises
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- There is no propagation delay, although it may be compensated for with a delay element for the output / feedback
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### Analysis
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1. Determine logic expressions for next state and output in terms of current state and input
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2. Create transition and flow tables
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3. Circle stable states (will lead to itself)
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4. Replace bits with letters
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5. Assign bit variables to avoid changing more than one input at a time (as it is undefined)
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To create a circuit:
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1. Create a state diagram
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2. Flow table
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3. Minimise state
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4. Excitation table
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5. Circuit
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### Reducing state
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1. Partition per [#Minimising state](#minimising-state)
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- *don't cares* are no longer equivalent unless both states have them in the same columns
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2. States are compatible if and only if, regardless of input:
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- their output is the same
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- their next state is the same, is stable, or are unspecified
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3. Merger diagram, identifying conflicts/compatible pairs
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4. Connect diagram, merging a subset (not all) of compatible states
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- states can only be in at most one subset
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5. Repeat
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### Avoiding races
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!!! definition
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- **Non-critical races** result in the same stable end state.
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- **Critical races** cause *problems*.
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- A **hazard** is unwanted switching due to unequal propagation delays.
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To avoid races: an $n$-dimensional cube with one vertex per state, ensuring that changes only move along one edge. If more states are needed to avoid this, they are automagically *unstable*.
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Alternatively, if $n\leq 4$, a state $A$ can be split into equivalent states $A1, A2$.
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1. Create a cube with $2n$ vertices
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2. Pairs must be adjacent
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3. Determine next states by following cube lines only
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Alternatively, each state can be assigned exactly one `1` bit, and transitions from one to another have `1`s at the states they transition between.
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### Hazards
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**Static-1/0 hazards** occur when output should stay constant, but suddenly flickers to the other. These can be fixed by covering minterms adjacent but not connected with another gate as an extra check.
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**Dynamic hazards** occur when outputs flip multiple times before stabilising. These can be avoided by switching everything to 2-term POS or SOP and fixing static hazards.
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## VHDL
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VHDL is a hardware schematic language.
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